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1

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger

Yoichi Sasaki, Kazuteru Namba, Hideo Ito

Journal:

Journal of Electronic Testing

Year:

2008

Language:

english

File:

PDF, 405 KB

english, 2008

2

[IEEE 2010 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) - Kyoto, Japan (2010.10.6-2010.10.8)] 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems - Single Event Induced Double Node Upset Tolerant Latch

Namba, Kazuteru, Sakata, Masatoshi, Ito, Hideo

Year:

2010

Language:

english

File:

PDF, 158 KB

english, 2010

3

Concurrent Error Detection of Binary and Nonbinary OLS Parallel Decoders

Namba, Kazuteru, Lombardi, Fabrizio

Journal:

IEEE Transactions on Device and Materials Reliability

Year:

2014

Language:

english

File:

PDF, 898 KB

english, 2014

4

A Single and Adjacent Symbol Error-Correcting Parallel Decoder for Reed–Solomon Codes

Namba, Kazuteru, Lombardi, Fabrizio

Journal:

IEEE Transactions on Device and Materials Reliability

Year:

2015

Language:

english

File:

PDF, 344 KB

english, 2015

5

High-Speed Parallel Decodable Nonbinary Single-Error Correcting (SEC) Codes

Namba, Kazuteru, Lombardi, Fabrizio

Journal:

IEEE Transactions on Device and Materials Reliability

Year:

2016

Language:

english

File:

PDF, 1.63 MB

english, 2016

6

Parallel decoding for burst error control codes

Eiji Fujiwara, Kazuteru Namba, Masato Kitakami

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

2004

Language:

english

File:

PDF, 1.43 MB

english, 2004

7

Unequal error control codes with two-level burst and bit error correcting capabilities

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

2004

Language:

english

File:

PDF, 882 KB

english, 2004

8

A class of systematic m-ary single-symbol error correcting codes

Kazuteru Namba, Eiji Fujiwara

Journal:

Systems and Computers in Japan

Year:

2001

Language:

english

File:

PDF, 177 KB

english, 2001

9

Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings

Kazuteru Namba, Eiji Fujiwara

Journal:

Systems and Computers in Japan

Year:

2007

Language:

english

File:

PDF, 261 KB

english, 2007

10

Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding

Kazuteru Namba, Yoshikazu Matsui, Hideo Ito

Journal:

Journal of Electronic Testing

Year:

2009

Language:

english

File:

PDF, 396 KB

english, 2009

11

Chiba Scan Delay Fault Testing with Short Test Application Time

Kazuteru Namba, Hideo Ito

Journal:

Journal of Electronic Testing

Year:

2010

Language:

english

File:

PDF, 649 KB

english, 2010

12

[IEEE 2010 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) - Kyoto, Japan (2010.10.6-2010.10.8)] 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems - Soft Error Tolerant BILBO FF

Namba, Kazuteru, Ito, Hideo

Year:

2010

Language:

english

File:

PDF, 160 KB

english, 2010

13

[IEEE 2012 21st Asian Test Symposium (ATS) - Niigata, Japan (2012.11.19-2012.11.22)] 2012 IEEE 21st Asian Test Symposium - NoC Dynamically Reconfigurable as TAM

Sbiai, Takieddine, Namba, Kazuteru

Year:

2012

Language:

english

File:

PDF, 395 KB

english, 2012

14

Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop

Kazuteru Namba, Takashi Katagiri, Hideo Ito

Journal:

Journal of Electronic Testing

Year:

2013

Language:

english

File:

PDF, 588 KB

english, 2013

15

[IEEE 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - New York City, NY, USA (2013.10.2-2013.10.4)] 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - Testing of switch blocks in TSV-reduced Three-Dimensional FPGA

Maebashi, Kouta, Namba, Kazuteru, Kitakami, Masato

Year:

2013

File:

PDF, 190 KB

2013

16

Extending Non-Volatile Operation to DRAM Cells

Wei Wei,, Namba, Kazuteru, Lombardi, Fabrizio

Journal:

Year:

2013

Language:

english

File:

PDF, 12.48 MB

english, 2013

17

Design of a Nonvolatile 7T1R SRAM Cell for Instant-on Operation

Wei, Wei, Namba, Kazuteru, Han, Jie, Lombardi, Fabrizio

Journal:

IEEE Transactions on Nanotechnology

Year:

2014

Language:

english

File:

PDF, 779 KB

english, 2014

18

[IEEE 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Austin, TX, USA (2012.10.3-2012.10.5)] 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Dual-edge-triggered FF with timing error detection capability

Namba, Kazuteru, Katagiri, Takashi, Ito, Hideo

Year:

2012

Language:

english

File:

PDF, 134 KB

english, 2012

19

[IEEE 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing (PRDC) - Tokyo, Japan (2010.12.13-2010.12.15)] 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing - Quantitative Evaluation of Integrity for Remote System Using the Internet

Kitakami, Masato, Konno, Hiroshi, Namba, Kazuteru, Ito, Hideo

Year:

2010

Language:

english

File:

PDF, 138 KB

english, 2010

20

[IEEE 2006 15th Asian Test Symposium - Fukuoka, Japan (2006.11.20-2006.11.20)] 2006 15th Asian Test Symposium - Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding

Namba, Kazuteru, Ito, Hideo

Year:

2006

Language:

english

File:

PDF, 3.75 MB

english, 2006

21

[IEEE 2010 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsin Chu, Taiwan (2010.04.26-2010.04.29)] Proceedings of 2010 International Symposium on VLSI Design, Automation and Test - A low-area and short-time scan-based embedded delay measurement using signature registers

Katoh, Kentaroh, Namba, Kazuteru, Ito, Hideo

Year:

2010

Language:

english

File:

PDF, 233 KB

english, 2010

22

[IEEE 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Austin, TX, USA (2012.10.3-2012.10.5)] 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Improving small-delay fault coverage for on-chip delay measurement

Zhang, Wenpo, Namba, Kazuteru, Ito, Hideo

Year:

2012

File:

PDF, 597 KB

2012

23

[IEEE 2009 Asian Test Symposium - Taichung, Taiwan (2009.11.23-2009.11.26)] 2009 Asian Test Symposium - A Delay Measurement Technique Using Signature Registers

Katoh, Kentaroh, Tanabe, Toru, Zahidul, Haque Md, Namba, Kazuteru, Ito, Hideo

Year:

2009

Language:

english

File:

PDF, 422 KB

english, 2009

24

[IEEE 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - New York City, NY, USA (2013.10.2-2013.10.4)] 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - A novel scheme for concurrent error detection of OLS parallel decoders

Namba, Kazuteru, Lombardi, Fabrizio

Year:

2013

Language:

english

File:

PDF, 1.46 MB

english, 2013

25

[IEEE 2008 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTVS) - Cambridge, MA, USA (2008.10.1-2008.10.3)] 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems - Soft Error Hardened FF Capable of Detecting Wide Error Pulse

Ruan, Shuangyu, Namba, Kazuteru, Ito, Hideo

Year:

2008

Language:

english

File:

PDF, 386 KB

english, 2008

26

[IEEE 2008 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTVS) - Cambridge, MA, USA (2008.10.1-2008.10.3)] 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems - Delay Fault Testability on Two-Rail Logic Circuits

Namba, Kazuteru, Ito, Hideo

Year:

2008

Language:

english

File:

PDF, 341 KB

english, 2008

27

[IEEE 2010 19th Asian Test Symposium (ATS) - Shanghai, China (2010.12.1-2010.12.4)] 2010 19th IEEE Asian Test Symposium - A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit

Katoh, Kentaroh, Namba, Kazuteru, Ito, Hideo

Year:

2010

Language:

english

File:

PDF, 251 KB

english, 2010

28

[IEEE 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC) - Shanghai, China (2009.11.16-2009.11.18)] 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing - Dependability Evaluation for Internet-Based Remote Systems

Kitakami, Masato, Katada, Akihiro, Namba, Kazuteru, Ito, Hideo

Year:

2009

Language:

english

File:

PDF, 141 KB

english, 2009

29

[IEEE 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) - Chicago, Illinois, USA (2009.10.7-2009.10.9)] 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Testing of Switch Blocks in Three-Dimensional FPGA

Hoshi, Takumi, Namba, Kazuteru, Ito, Hideo

Year:

2009

Language:

english

File:

PDF, 381 KB

english, 2009

30

[IEEE 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Amsterdam, Netherlands (2014.10.1-2014.10.3)] 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance

Wei, Wei, Lombardi, Fabrizio, Namba, Kazuteru

Year:

2014

Language:

english

File:

PDF, 295 KB

english, 2014

31

[IEEE 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) - Rome, Italy (2007.09.26-2007.09.28)] 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007) - Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing

IKEDA, Takashi, NAMBA, Kazuteru, ITO, Hideo

Year:

2007

Language:

english

File:

PDF, 1.08 MB

english, 2007

32

[IEEE 2008 14th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC) - Taipei, Taiwan (2008.12.15-2008.12.17)] 2008 14th IEEE Pacific Rim International Symposium on Dependable Computing - Path Delay Fault Test Set for Two-Rail Logic Circuits

Namba, Kazuteru, Ito, Hideo

Year:

2008

Language:

english

File:

PDF, 182 KB

english, 2008

33

[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit

Sasaki, Yoichi, Namba, Kazuteru, Ito, Hideo

Year:

2006

Language:

english

File:

PDF, 258 KB

english, 2006

34

[IEEE TENCON 2013 - 2013 IEEE Region 10 Conference - Xi'an, China (2013.10.22-2013.10.25)] 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013) - Delay measurement of dual-rail asynchronous circuits for small-delay defect detection

Zhang, Wenpo, Namba, Kazuteru, Ito, Hideo

Year:

2013

Language:

english

File:

PDF, 557 KB

english, 2013

35

[IEEE 2014 IEEE 12th International Conference on Solid -State and Integrated Circuit Technology (ICSICT) - Guilin, China (2014.10.28-2014.10.31)] 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Area overhead reduction for small-delay defect detection using on-chip delay measurement

Zhang, Wenpo, Namba, Kazuteru, Ito, Hideo

Year:

2014

Language:

english

File:

PDF, 1.11 MB

english, 2014

36

Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM)

Namba, Kazuteru, Lombardi, Fabrizio

Journal:

IEEE Transactions on Computers

Year:

2015

Language:

english

File:

PDF, 566 KB

english, 2015

37

[ACM Press the 24th edition of the great lakes symposium - Houston, Texas, USA (2014.05.21-2014.05.23)] Proceedings of the 24th edition of the great lakes symposium on VLSI - GLSVLSI '14 - New 4T-based DRAM cell designs

Wei, Wei, Namba, Kazuteru, Lombardi, Fabrizio

Year:

2014

Language:

english

File:

PDF, 1.07 MB

english, 2014

38

[ACM Press the 25th edition - Pittsburgh, Pennsylvania, USA (2015.05.20-2015.05.22)] Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15 - Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits

Lombardi, Fabrizio, Wei, Wei, Namba, Kazuteru

Year:

2015

Language:

english

File:

PDF, 842 KB

english, 2015

39

[IEEE 2015 16th International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2015.3.2-2015.3.4)] Sixteenth International Symposium on Quality Electronic Design - A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement

Katoh, Kentaroh, Namba, Kazuteru

Year:

2015

Language:

english

File:

PDF, 296 KB

english, 2015

40

[IEEE 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO) - Rome, Italy (2015.7.27-2015.7.30)] 2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO) - Hybrid designs for non-volatile embedded memory cells

Wei, Wei, Lombardi, Fabrizio, Namba, Kazuteru

Year:

2015

Language:

english

File:

PDF, 301 KB

english, 2015

41

[ACM Press the 26th edition - Boston, Massachusetts, USA (2016.05.18-2016.05.20)] Proceedings of the 26th edition on Great Lakes Symposium on VLSI - GLSVLSI '16 - Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level

Wei, Wei, Namba, Kazuteru, Lombardi, Fabrizio

Year:

2016

Language:

english

File:

PDF, 813 KB

english, 2016

42

[IEEE 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Storrs, CT, USA (2016.9.19-2016.9.20)] 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Construction of a soft error (SEU) hardened Latch with high critical charge

Ueno, Hiroki, Namba, Kazuteru

Year:

2016

Language:

english

File:

PDF, 896 KB

english, 2016

43

A Calibration Technique for DVMC with Delay Time Controllable Inverter

Cui, Ri, Namba, Kazuteru

Journal:

IPSJ Transactions on System LSI Design Methodology

Year:

2016

Language:

english

File:

PDF, 874 KB

english, 2016

44

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability

Katoh, Kentaroh, Namba, Kazuteru, Ito, Hideo

Journal:

IPSJ Transactions on System LSI Design Methodology

Year:

2008

Language:

english

File:

PDF, 920 KB

english, 2008

45

Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture

Matsumoto, Kiyonori, Namba, Kazuteru, Ito, Hideo

Journal:

IPSJ Transactions on System LSI Design Methodology

Year:

2011

Language:

english

File:

PDF, 739 KB

english, 2011

46

Construction of BILBO FF with Soft-Error-Tolerant Capability

NAMBA, Kazuteru, ITO, Hideo

Journal:

IEICE Transactions on Information and Systems

Year:

2011

Language:

english

File:

PDF, 222 KB

english, 2011

47

On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction

Namba, Kazuteru, Lombardi, Fabrizio

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2018

Language:

english

File:

PDF, 1.53 MB

english, 2018

48

A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits

Lombardi, Fabrizio, Namba, Kazuteru

Journal:

IEEE Transactions on Computers

Year:

2018

Language:

english

File:

PDF, 894 KB

english, 2018

49

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

ZHANG, Wenpo, NAMBA, Kazuteru, ITO, Hideo

Journal:

IEICE Transactions on Information and Systems

Year:

2014

Language:

english

File:

PDF, 752 KB

english, 2014

50

Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability

RUAN, Shuangyu, NAMBA, Kazuteru, ITO, Hideo

Journal:

IEICE Transactions on Information and Systems

Year:

2009

Language:

english

File:

PDF, 467 KB

english, 2009

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